Design And Evaluation Of Binary-Tree Based Scalable 2d And 3d Network-On-Chip Architecture

Network-on-Chip (NoC) has been developed as a most prevailing innovation in the paradigm of communication-centric technology. It solves the limitations of bus-based systems, with the incorporation of 3D IC technology, and it reduces packaging density and improves performance of Multiprocessor System-on-Chip. There is need of suitable NoC topology for these applications and desired performances. This paper proposes a scalable binary tree-based topology for 2D and 3D NoCs. The average degree of the proposed network is reduced around 40% of the torus whereas the diameter also reduced significantly, as compared to other topologies.[GRAPHICS]