Area-efficient CMOS implementation of NCL gates for XOR-AND/OR dominated circuits
2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)(2017)
摘要
Null conventional logic units are the most important logic units in asynchronous circuits. This paper presents an area-efficient CMOS implementation of Null Conventional Logic (NCL) gates for XOR-AND/OR dominated asynchronous circuits. These optimization of logic gates are based on Binary Decision Diagram (BDD) that produces 25% and 14.29% fewer transistor counts for the proposed logic topology of XOR and AND/OR respectively. Thus, giving a reduced area of more than 14% compared with the conventional NCL logic circuits. The simulation results show the delay and energy consumption can give a reasonable result as compared to conventional approach.
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关键词
Null Convention Logic(NCL),C-element,Dual-rail signal,CMOS gate design
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