Study of Counter-Pulse (CP) Programming Method to Improve the Vt Distribution for 3D Charge-Trapping NAND Flash Devices
international memory workshop, 2018.
The charge-trapping devices used in 3D NAND Flash often possess certain fast initial charge loss behaviors, leading to degraded programming distributions. A possible design method to improve the programming distribution is to insert an additional programming phase named as counter-pulse (CP), which is applied immediately after +FN program...More
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