Comparative Study Of Sub-Vt Sram Bitcells Based On Noise-Margin-Aware Design

Various bitcells were proposed for sub- threshold (sub-Vt) SRAM design with bit interleaving to deal with multi-bit soft errors. Each proposed bitcell uses its own design strategy, where the half-select issue in hit-interleaved cells has been addressed with distinct tradeoffs. However, a design strategy for one cell may not be practical for another, and it is not trivial to compare these cells just by re-designing them with a specific flow. This paper presents a comparative analysis and design of state-uof-the-art hit-interleaved SRAM bitcells with a noise-margin-(NM-) aware design approach, which accounts the NM demand in addition to minimizing the cell area. We also disclose complete bitcell design flows, beginning from step-by-step transistor sizing, noise margin evaluation, to the exploration of the minimum operating voltage (Vmin).