Simulation Study on the Design of Sub- $kT/q$ Non-Hysteretic Negative Capacitance FET Using Capacitance Matching

In this paper, approaches to obtain the sub- kT/q non-hysteretic operation mode in negative capacitance (NC) field-effect-transistors for a wide band of applied gate voltages, using capacitance matching, were systematically investigated using TCAD simulation. Unlike certain previous studies, in which the desired operation conditions were received for specific structures and materials, this study presents for the first time a general approach for matching arbitrary MOSFETs with various ferroelectric (FE) materials. This study shows that depending on the initial capacitance matching which represents the best possible subthreshold slope for the preliminary chosen base structure and FE material, any further optimization process can be different. Additionally, for the first time, FE materials were grouped with respect to the shape of their C–V curves in the NC region. This paper shows that with respect to the base structure, certain types of FEs are more preferable to obtain the sub- kT/q operation in a non-hysteretic manner for the wide band of applied voltages. In addition, the impacts of various parameters including the depletion capacitance, supply voltage, gate oxide capacitance, buried oxide capacitance on the capacitance matching were systematically investigated.