Assembly Process Development of Ultra Large Scale 3D Stacking with Transmission Circuits Via TSVs

This paper introduces the assembly process development of ultra large scale 3D stacking, using both CFD and thermo-mechanical simulations. The height of C4 bumps in 3D stacking was optimized for satisfactory flux cleaning performance and fatigue lifetime estimates by controlling the minimum height and adding the necessary volume of solder to each C4 bump. With the procedure developed for stacking, a prototype processor was successfully mounted on a substrate and then assembled on a printed wiring board. To validate interconnections from the top chip to the printed wiring board, a test pattern program was run and signal transmission in multiple lanes, where the top and bottom chips communicated with each other through TSVs and micro bumps, was confirmed at speeds of over 1 GHz; in addition, the connectivity was confirmed with daisy chain interconnections.