An 802.11a/b/g/n Digital Fractional-N PLL With Automatic TDC Linearity Calibration for Spur Cancellation.

A fractional-N digital phase-locked loop (PLL) architecture with low fractional spur is presented in this paper. A 2-D Vernier time-to-digital convertor (TDC) is implemented to achieve wide detection range with fine resolution. The TDC is calibrated automatically utilizing the ramp signal generated from the fractional-N accumulator for optimal linearity. A digi-phase spur cancellation technique wi...