Development of a stacking technology for large-sized chips using non-conductive film

A chip stacking process technology using high mass productivity non-conductive film (NCF) has been developed, with assumptions for the central processing unit (CPU) in high-end servers. With this process, a 23 mm by 23 mm chip with a bump pitch of 40 μm was successfully stacked onto another, and 296,000 bumps were jointed in total. In the development of the chip stacking process, in order to measure NCF behavior in the thermo compression flip chip (TCFC) bonding process, the head position detecting mechanism of a flip chip bonder (FCB) measured NCF deformation between the chip and a bare silicon plate in real time. During the measurement, the bonding head applied a constant load to the NCF, and its temperature went up. In order to observe the effect of chip size, NCF deformation was measured at three chip sizes. The amount of deformation of a large-sized chip was found to be less than that of a small-sized chip under the same pressure applied to the chips. This result revealed a limitation of the chip stacking process for large-sized chips using NCF. In addition, variations in bump height or silicon thickness occurring in the LSI manufacturing process were found to cause various problems in the chip stacking process using NCF. These problems were solved using a special bonding tool. Moreover, to suppress voids, the behavior of voids was observed, which found voids remaining in the chip corners. Shaping NCF in the X-shape suppressed these corner voids.