Si-Passivated Ge Nmos Gate Stack With Low D-It And Dipole-Induced Superior Pbti Reliability Using 3d-Compatible Ald Caps And High-Pressure Anneal

We demonstrate a Si-passivated Ge nMOS gate stack with DIT of similar to 5x1010 cm(-2)eV(-1) around midgap and unnoticeable C-V hysteresis at an operating condition (oxide trap density of similar to 1x10(8) cm(-2) at V-ov/CET=3.5 MV/cm). Insertion of a 3D-compatible thin ALD LaOx, MgOx and LaSiO layer at the interface between HfO2 and SiO2/Si/Ge improves PBTI reliability thanks to the interface dipole-induced band engineering. The high DIT of Si-passivated Ge nFET is dramatically reduced by similar to 40x around midgap using a combination of the LaSiO insertion and a H-2 high-pressure anneal (HPA). These key gate stack technologies realize further improvements in mobility (similar to 50% at peak) and PBTI reliability (V-ov=0.32 V for 10 years) of Si-passivated Ge nFETs.