Towards On-Line Estimation Of Bti/Hci-Induced Frequency Degradation

This work proposes a new bottom-up approach for on-line estimation of circuit performance loss due to BTI/HCI effects. Built on the top of device-level models, it takes into account all factors that impact global circuit aging, namely, process, topology, workload, voltage and temperature variations. The proposed model is fed by voltage and temperature monitors that on-line track dynamic variations. This allows an accurate assessment of the evolution of the circuit critical path delays during its operation. Its accuracy is evaluated here on two circuits implemented in 28nm FD-SOI technology.