Energy-Efficient Reconfigurable Hardware Accelerators For Data-Intensive Applications

Energy-efficiency has emerged as a major barrier to performance scalability in modern computers. For conventional computers as well as external hardware accelerators, such as Field Programmable Gate Arrays (FPGAs) and General Purpose Graphics Processing Units (GPGPUs), the data transfer between on-chip computing elements and off-chip memories contribute significantly to the overall power consumption, while limiting scalability. An effective solution is to enable data processing in offchip memory, reducing data transfer bandwidth and energy requirements. In this paper, we describe a novel hardware acceleration framework that transforms high-density memory arrays into configurable computing resources to accelerate data-intensive tasks. This framework exploits the standard regular block-based memory architectures to create a spatially connected array of lightweight processors with customized hierarchical interconnects for in-accelerator data transfer. One general purpose Flash memory based accelerator and three of its domain-specific variants are described in details. Application kernels from different domains are mapped to these accelerator frameworks, and design overheads and energy-efficiency are carefully estimated. All accelerators show significant improvement in energy-efficiency and performance scalability compared to more conventional computing and acceleration platforms. Architecture-level design principles and application mapping process to these platforms are described.