Accelerating Deterministic Bit-Stream Computing with Resolution Splitting

Deterministic approaches to stochastic computing (SC) have been recently proposed to produce completely accurate results with stochastic logic. Long processing time is the main limitation of these methods when a deterministic zero error rate output is expected. For instance, when multiplying two n-bit precision input values, a processing time of $2^{2n}$ cycles is required. This long processing time makes the current deterministic approaches of SC inefficient for many applications. In this work, we propose an acceleration method based on resolution splitting to mitigate this long latency. The result is an exponential reduction in the processing time at the cost of some increase in the hardware area. The exponential reduction in the processing time results in a significant reduction in energy consumption. Synthesis results show that for the common 2-input multiplier, the proposed design decreases the energy consumption more than $\pmb{2000}\times$ compared to the prior state-of-the-art deterministic bit-stream-based design.