Simulation Based Assessment of SRAM Data Retention Voltage

With the continued scaling of MOSFET feature size, reducing the SoC power consumption has become one of the main challenges for the semiconductor industry. Lowering the data retention voltage $(\mathrm{V}_{\mathrm{ret}})$ can significantly improve the SRAM standby power, which has become one of the dominant components of the overall system power consumption. Therefore, an accurate assessment of SRAM $\mathrm{V}_{\mathrm{ret}}$ is of critical importance to determine the lowest $\mathrm{V}_{\mathrm{ret}}$ specification for the SRAM array that still meets the overall product yield target. In this work, the data retention voltage distribution of a 22nm 6T SRAM array is studied through variation aware transient SPICE simulation and compared to Si data. The results show that parametric device variability based intrinsic simulation is insufficient to estimate the data retention voltage of SRAM array. The effect of gate oxide short (GOS), an extrinsic gate leakage mechanism, on the $\mathrm{V}_{\mathrm{ret}}$ distribution of SRAM array is studied, and it indicates that data retention voltage is especially sensitive to gate oxide shorts. It is shown that gate-drain oxide short and pull-down (PD) transistor gate-source oxide short are the most probable extrinsic mechanisms limiting the yield of the 22nm SRAM array. By accounting both intrinsic and extrinsic effects, an excellent agreement to measured $\mathrm{V}_{\mathrm{ret}}$ distribution is demonstrated. The methodology validated in this work could be applied to other technology nodes as well, to get a better $\mathrm{V}_{\mathrm{ret}}$ yield estimation.