A Comparative Study Between FinFET and CMOS-Based SRAMs under Resistive Defects

Due to several factors, such as Process Variations (PV), increased leakage current, Random Dopant Fluctuation (RDF), and mainly the Short-Channel Effect (SCE), the miniaturization of planar CMOS transistors reached its limit at the 22nm node. To continue the miniaturization process via technology down-scaling, while preserving system reliability and performance, FinFET devices arise as an alternative to substitute the CMOS transistors. Additionally, Static Random-Access Memories (SRAMs) have been increasingly occupying a great part of Systems-on-Chips (SoCs) silicon area. Designed to reach densities at the limit of the manufacturing process, make this component susceptible to manufacturing defects, including resistive defects. Such defects can escape traditional manufacturing tests, because they may cause dynamic faults during circuits’ lifetime. In this context, a comparison between a 20nm FinFET-based SRAM block and a commercial 65nm CMOS-based SRAM block focusing on resistive defects is carried out. The behavior of defective cells operating over different temperature sets has been investigated by means of SPICE simulations. Results show an expressively higher occurrence of dynamic faults induced by resistive defects in FinFET-based memories when compared to CMOS technology.