InAs FinFETs With $ extrm {H}_{mathrm {fin}}=20$ nm Fabricated Using a Top–Down Etch Process

IEEE Electron Device Letters(2016)

引用 24|浏览58
暂无评分
摘要
We report the first demonstration of InAs FinFETs with fin width Wfin in the range 25-35 nm, formed by inductively coupled plasma etching. The channel comprises defect-free, lattice-matched InAs with fin height Hfin = 20 nm controlled by the use of an etch stop layer incorporated into the device heterostructure. For a gate length Lg = 1 μm, peak transconductance gm,peak = 1430 μS/μm is measured at...
更多
查看译文
关键词
Logic gates,FinFETs,Performance evaluation,Substrates,Indium compounds,Surface treatment,High K dielectric materials
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要