Implementation of a 256x8 Sector Size SRAM grid with memory write speedup on CeidMem library

In this work, the implementation of a static memory grid, consisting of sectors with size 256×8 bits, is presented. The grid supports memory write speedup leading to a minimized write pulse of at least 5 times than the typical implementation of static memories. All implementations have been done using the CeidMem Static Memory Library and the simulation results of the behavior of the grid is presented and analyzed.