Device optimization on gate oxide and spacer dielectric permittivity for “well-tempered” nanoscale MOSFET

We propose a new optimized design strategy by considering the correlated effects of high-κ gate oxide and spacer dielectric on GIDL and DIBL in nanoscale MOSFET. By investigating the transition of GIDL mechanism from vertical to lateral in 32 nm nMOS with abrupt and high drain extension doping, the lateral GIDL is suppressed by 10 ^-4 with high-κ spacer (e.g. TiO ₂ ). DIBL is also suppressed below 100 mV/V by taking relatively lower-κ gate oxide (e.g. HfO ₂ ) than high-κ spacer.