A 14-Bit 8-Column Shared Sar Adc For 640x512 Irfpa

This paper presents a new structure of column-level successive approximation register (SAR) analogue-to-digital converter (ADC) for Infrared Focal Plane Array. In this design, each column has a capacitance array and each comparator and SAR logic block are shared by 8 columns. By using this shared structure, we achieved smaller silicon area, lower power dissipation and lower noise. And shared structure leaves enough space for signal and control wires of ADC blocks, therefore relieves the mutual disturbance among wires. Also, correlated switches are used to cancel the offset generated by charge injection. The conversion accuracy of the proposed ADC is 14 bits and is used for a 640x512 array with a frame rate of 50Hz.