An Updated Front-End Data Link Design For The Phase-2 Upgrade Of The Atlas Tile Calorimeter

We present a new design for the advanced Link Daughter Board (DB) for the front-end electronics upgrade of the ATLAS hadronic Tile Calorimeter. The DB provides control, configuration and continuous ADC readout for the front-end through bi-directional multi-GB/s optical links with the off detector readout system. The DB will operate in high luminosity LHC conditions with limited detector access, so the design is fault tolerant with a high level of redundancy to avoid single-point failure modes. The new design is based on the new Xilinx Kintex Ultrascale+ FPGA family, which provides improved high-speed link timing performance and radiation tolerance, as well as better signal compatibility with the CERN-developed GBTx link and timing distribution ASICs. Two GBTx ASICs each provide redundant phase-adjusted, LHC synchronous clocks, parallel control buses and remote JTAG configuration access to the two FPGAs on the DB.