Reliability- and performance-driven mapping for regular 3D NoCs using a novel latency model and Simulated Allocation

Network-on-Chip (NoC) -based communication architecture is promising in addressing the communication bottlenecks in current and future multicore processors. In this work, we consider the application-specific mapping problem and electromigration (EM) -induced through-silicon via (TSV) reliability issue in tile-based three-dimension (3D) NoC architectures. In 3D NoCs, network contention may result in unacceptable communication delay among the processing cores and thus has significant effect on the system performance. So we propose a new latency model for the routers which characterizes the network contentions among different traffic flows from sharing of network resources. Then we solve the core mapping problem by a fast while efficient stochastic algorithm called Simulated Allocation (SAL), which integrates our new latency model and also aims to optimize the communication power, latency in the mapping procedure. After that, we use an incremental method to optimize the reliability of the TSVs. Experimental results show that, contention-aware model (CAM) has 25% larger network latency than our latency model; compared with particle swarm optimization (PSO), our SAL algorithm can achieve 7% less power with about 7.5 × run-time speedup; as for reliability, our method can achieve better results (up to 10 × increase in terms of the void nucleation time (VNT)) with 7.64% increased latency.