Reconfigurable FPGA Implementation of the AVC Quantiser and De-quantiser Blocks

As image and video resolution continues to increase, compression plays a vital role in the successful transmission of video and image data over a limited bandwidth channel. Computation complexity, as well as the utilization of resources and power, keep increasing when we move from the H264 codec to the H265 codec. Optimizations in each particular block of the Advanced Video Coding (AVC) standard significantly improve the operating frequency of a hardware implementation. In this paper, we designed parametrized reconfigurable quantiser and de-quantiser blocks of AVC through dynamic circuit specialization, which is different from traditional reconfiguration of FPGA. We implemented the design on a Zynq-SoC board, which resulted in optimizations in resource consumption of 14.1% and 20.6% for the quantiser and dequantiser blocks respectively, compared to non-reconfigurable versions.