Voltage Controlled Magnetic Tunnel Junction Based 3d-Crosspoint Memory With Step Shaped Pulse For Reliable Write Operation

Recently, STT-MRAM has been commercialized. MRAM with voltage controlled magnetic tunnel junction (VC-MTJ) has been expected as a post-STT-MRAM memory with faster speed and lower power [1–5]. Since read operation for VC-MTJ uses TMR as other MRAMs, conventional read can be used. On the other hand, VC-MTJ has specific write feature where write error rate (WER) is oscillatory dependent on pulse width. Hence, WER reduction for VC-MTJ is crucial. Previous studies have shown VC-MTJ applications for cache and main memory [6, 7]. Recently, storage class memory (SCM) has been introduced to mitigate memory gap between storage and main memory [8]. SCM is also a candidate for VC-MTJ utilization, since VC-MTJ has unipolar write suitable for 3D-crosspoint (3DX) configuration. This is the first paper to describe feasibility of VC-MTJ for SCM applications from the viewpoint of designs for memory cells and circuits. Typical SCM is characterized by 3DX structure with two-terminal selector device(SD) (Fig. 1(a)). SD has longer switching time than VC-MTJ [9–11]. Here, switching time variations of SD changes write pulse width of VC-MTJ that causes WER degradation. This is a major issue. To solve this, we propose a novel two-step pulse write method as described later. We evaluate WER improvement with this method by advanced circuit simulation. We further analyze WER reduction by interconnect and write driver. Major requirement for SD in 3DX memory is high on-off ratio to suppress sneak leakage current. Various SD have been intensively developed [9]. Among them, threshold type selector is considered to be promising due to large on-off ratio [10, [11] and several ten ns switching time. Figure 1(b) schematically shows conventional write pulse voltage $( mathrm {V}_{mathrm {W}})$, voltage across SD $( mathrm {V}_{mathrm {SEL}})$ and voltage across MTJ $( mathrm {V}_{mathrm {MTJ}})$. Initially, write voltage is applied to only SD, since off-state SD has much higher resistance than MTJ. After SD switches into on-state, write voltage is applied to only MTJ, since on-state SD has much lower resistance than MTJ. As SD has switching time variation, pulse width of $mathrm {V}_{mathrm {MTJ}}( mathrm {T}_{mathrm {MTJ}})$ varies and WER degrades severely. To suppress WER degradation, we propose two-step write pulse method (Fig. 1(c)), where write pulse has two voltage steps. First voltage is only for switching of SD and smaller than switch voltage of MTJ. Second voltage is for switching of MTJ. In this method, switch time variation of SD affects only the first voltage time, and not affects the second voltage time, $mathrm {T}_{mathrm {MTJ}}$. To evaluate WER with a proposed method, we firstly obtained $mathrm {V}_{mathrm {MTJ}}$ shape in 3DX arrays by circuit simulation based on 2X nm 3DX memory [8]. WER was then calculated using the $mathrm {V}_{mathrm {MTJ}}$ shape by Monte-Carlo simulation [3]. Figure 2 (a) shows WER of VC-MTJ in 3DX when 1024 bit cells are connected to a word line (WL). We calculated WER for various WL interconnect thickness, assuming interconnect material is tungsten [8]. The interconnect thickness was selected between 40 nm and 80 nm, since that of 3DX memory products is about 40 nm to 65 nm [8]. We also assumed damping constant, a = 0.025 and, diameter, f = 20 nm for MTJ, and external magnetic field to in-plane direction, $mathrm {H}_{mathrm {ext}}=152.6$ Oe, so that switching time is about 1ns. Fig. 2(a) also shows WER when an idealistic trapezoidal pulse having no interconnect delay is directly applied to VC-MTJ for reference. These results indicate that as interconnect becomes thicker, WER of VC-MTJ is improved, and it becomes closer to a target WER for SCM (~1×10 −4 ). This reason is that the decrease in pulse rise and fall time by resistance reduction of interconnects. However, increasing interconnect thickness might make etching process difficult and obstacles further memory cell scaling. In case that interconnect thickness cannot be increased, we propose dual wordline (WL) driver circuit (DWD) shown in Fig. 2(b). When conventional single driver circuit is used for each WL, pulse distortion is largest at the other end. By driving WL from both ends using DWD, pulse rise and fall time become smaller than conventional ones. In this case, difference in activation time $( mathrm {t}_{mathrm {delay}})$ between the two WL drivers degrades WER (Fig. 2(c)), as shown in Fig. 2(d). When $mathrm {t}_{mathrm {delay}}$ is larger than 200 ps, WER becomes larger than single driver case. Therefore, we have to design interconnects and drivers so as $mathrm {t}_{mathrm {delay}}$ to be ~0s. WER is, then, almost the same as that of direct pulse application, as shown in Fig. 2(d). As a result, DWD circuit can reduce WER considerably close to a target WER for SCM (~1×10 −4) . These results thus indicate that WER of VC-MTJ for 3DX memory can be improved by proposed circuit designs. Figure 2(e) compares write performance of various nonvolatile memories, which indicates VC-MTJ is superior to others, since it has higher-speed and lowerpower write with higher-endurance compared with others. This work was partly supported by the ImPACT Program of the Council for Science, Technology and Innovation (Cabinet Office, Government of Japan). The authors would like to thank Yoichi Shiota for his contributions to VC-MTJ.