Two-level DLL with Femtosecond Added Jitter for a Low Power 20 GS/s Sampling ASIC

Vertex detectors in high luminosity particle colliders are subject to high hit rates leading to high occupancies. The proposed Timing Vertex Detector (TVD) is a potential solution that requires a readout application specific integrated circuit (ASIC) that measures pulse arrival times with a timing resolution in the range of 100 fs or less. Present efforts are centered on the development of such an ASIC, called the RFpix. One of the critical requirements is low added jitter. In this paper, we present results of the study on added jitter and jitter propagation in inverter chains for a 130 nm technology node. Furthermore, we propose a novel fully differential two-level delay-locked loop (DLL) circuit for the RFpix prototype with a simulated (layout parasitics included) worst case added jitter of 28 fs.