An In-Memory-Computing Design of Multiplier Based on Multilevel-Cell of Resistance Switching Random Access Memory

Due to the Von Neumann bottleneck, in-memory-computing, as a new architecture, has drawn considerable attention and is becoming an candidate of next generation electronics system. It presents an inmemory-computing approach for multiplier design based on Multilevel-cell (MLC) of Resistive random access memories (RRAMs). The paper proposes a Look-up-table (LUT) operations to optimize the speed, area...