Statistical Variability Simulation Of Novel Capacitor-Less Z2fet Dram: From Transistor To Circuit

The downscaling of traditional DRAM [1] is facing challenges due to the presence of external capacitor. Z2FET [2–5] has been demonstrated as a promising DRAM candidate eliminating theneed for external capacitor. In the past, attention was focused on the optimization of device structure [5] and fabrication process [2] without paying much attention to the Statistical (local) Variability (SV) which is crucial for any memory technology. In this paper, a novel simulation methodology is proposed and the SV of DRAM Memory Window (MW) is investigated systematically. It is found that SV of MW is dominated by Metal Gate Granularity (MGG) coming from the Gated-SOI region of the Z2FET. Although Random Discrete Dopant (RDD) induced variations in the threshold voltage (Vth) has larger spread in the Intrinsic-SOI part, it has no significant effect on the overall Z2FET characteristics. Based on the proposed methodology, SV of MW at different process corners has also been studied. Results reveal the necessity for further process optimization due to the best corner giving rise not only to larger average MW but also less variations. Furthermore, circuit level read performance (including the variability) of a Z2FET-based memory cell have been evaluated. All these findings could guide the further performance optimization from both device and memory cell circuit point of view for Z2FET-based volatile memory product development.