Finfet And Nanowire-Fet Device Design And Integration: Feol Challenges And Solutions

Scaling of high-perfoii lance logic devices is essentially driven by two requirements. Low leakage and high drive current. Here we investigate select issues and solutions: (i) Diffusion in nano-structures; (ii) SD/E doping requirements and their implications for doping solutions; (iii) Wrap-Around-Contact integration challenges. We do this by using a "virtual" fab, i.e. by employing Technology Computer Aided Design tools to mimic closely the processing and electrical testing in a real, physical fab, in particular explicitly modeling the doping processes such as implant and diffusion.