High Performance Ingaas Gate-All-Around Nanosheet Fet On Si Using Template Assisted Selective Epitaxy

We report InGaAs gate-all-around nanosheet NFETs on Si substrate using template-assisted-selective-epitaxy (TASE) and a gate-last process with thermal budget advantages. Compared to our early report of the TASE process, in this paper we demonstrate that TASE can be scaled to a channel thickness of similar to 10 nm, which enables short gate devices without significant leakage. The defects and composition of the fabricated nanosheet FETs are also investigated. Enabled by this VLSI compatible process and a novel high-pressure deuterium annealing process, our 39 nm-L-g device shows a peak g(m) of 1.37 mS/mu m, a subthreshold slope in saturation of 72 mV/decade, and an I-on of 355 mu A/mu m at 0.5 V V-gs, the highest among reported sub-50 nm-L-g III-V FETs on Si.