Efficient FPGA implementation of high speed digital delay for wideband beamforming using parallel architectures

In this paper, the authors present an FPGA implementation of a digital delay for beamforming applications. The proposed digital delay is based on a new architecture about the Parallel FIR Filter which is used to describe the Parallel Farrow Filter. Such architecture allows to reach very high processing rate with wideband signals and it is suitable to be used along with Time-Interleaved Analog to Digital Converters (TI-ADC).