A Highly Scalable, Time-Based Capless Low-Dropout Regulator Using Master-Slave Domino Control

An ultra-low quiescent current capacitor-less low-drop out (LDO) regulator is proposed in this paper. The LDO is designed using domino control which automatically increases or decrease the drive strength based on load current. Quiescent current of the proposed LDO also varies with load current hence current consumption is minimized under light load condition. The proposed LDO architecture is fully scalable and can be easily scaled up for higher load currents with almost no design efforts. Implemented in TSMC-65nm, it uses only 1pF of on-chip compensation capacitor and consumes a quiescent current of 11.5 mu A. For an input of 1.2 V and output of 0.9V to 1.1V, settling time of <200ns with undershoot/overshoot of 62mV/40mV for 0-5mA in 100ns load step is achieved 1pF output capacitor.