A Power Efficient Output Capacitor-Less LDO Regulator with Auto-Low Power Mode and Using Feed-Forward Compensation

2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID)(2019)

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摘要
An output capacitor-less low-drop out (LDO) regulator using a feed-forward compensation is presented in this paper. The power stage; implemented using flipped-voltage-follower (FVF) stage along with the feed-forward compensation stabilizes the LDO for the entire range of load current and load capacitor. The LDO uses only 1pF of compensation capacitor and consumes quiescent current of 28μA in active mode and 3μA in low power (LP) mode. A load current sensor is used to sense ultra-low power and automatically switch to LP mode. The proposed LDO was implemented in TSMC-65nm for an input of 1.2 V, output of 0.9V to 1.1V and achieves settling time of <;1μs with undershoot/overshoot of ~250mV for 10mA load current.
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关键词
feed-forward compensation, flipped voltage follower, capless LDO, low power mode
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