Neuadc: Neural Network-Inspired Rram-Based Synthesizable Analog-To-Digital Conversion With Reconfigurable Quantization Support

2019 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)(2019)

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摘要
Traditional analog-to-digital converters (ADCs) employ dedicated analog and mixed-signal (AMS) circuits and require time-consuming manual design process. They also exhibit limited reconfigurability and are unable to support diverse quantization schemes using the same circuitry. In this paper, we propose NeuADC -an automated design approach to synthesizing an analog-to-digital (A/D) interface that can approximate the desired quantization function using a neural network (NN) with a single hidden layer. Our design leverages the mixed-signal resistive random-access memory (RRAM) crossbar architecture in a novel dual-path configuration to realize basic NN operations at the circuit level and exploits smooth bit-encoding scheme to improve the training accuracy. Results obtained from SPICE simulations based on 130nm technology suggest that not only can NeuADC deliver promising performance compared to the state-of-art ADC designs across comprehensive design metrics, but also it can intrinsically support multiple reconfigurable quantization schemes using the same hardware substrate, paving the ways for future adaptable application-driven signal conversion. The robustness of NeuADC's quantization quality under moderate RRAM resistance precision is also evaluated using SPICE simulations.
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关键词
reconfigurable quantization support,ADCs,time-consuming manual design process,diverse quantization schemes,automated design approach,analog-to-digital interface,desired quantization function,single hidden layer,design leverages,basic NN operations,SPICE simulations,comprehensive design metrics,multiple reconfigurable quantization schemes,future adaptable application-driven signal conversion,moderate RRAM resistance precision,analog-to-digital converters,dual-path configuration,NeuADC quantization quality,neural network-inspired RRAM-based synthesizable analog-to-digital conversion,smooth bit-encoding scheme,mixed-signal resistive random-access memory crossbar architecture
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