An Improved Hardware Architecture for Integer-Pixel Motion Estimation in AVS3.

To achieve better video compression performance over previous video coding standards, the third-generation audio video coding standard (AVS3) has been developed. However, the Enhanced Predictive Zonal Search (EPZS) algorithm served as the Integer-Motion Estimation (IME) technique in reference code is not suitable for hardware video encoders due to its poor data flow regularity. In this paper, we proposed a Coding Tree Unit (CTU) level hardware-friendly IME algorithm and its hardware architecture for AVS3. Besides, the algorithm and its hardware architecture are also suitable for other video codec standard hardware encoders. Compared with the EPZS algorithm of AVS3, the proposed IME algorithm reduces computation consumption of time up to 75.24%, while coding performance loss only suffers 0.56%. Furthermore, the architecture is implemented on Verilog hardware description language and synthesized by Synopsys Design Compiler with SMIC 14nm CMOS standard cell library. The architecture includes about 1120K gates and the size of on-chip memory is 224KB. The amount of hardware resource consumption is acceptable. To meet the requirement of video encoding of 4K@60FPS in real-time, the latency needs less than 6379 cycles. 4722 cycles are required for executing the IME. The maximum working frequency of the designed IME circuit is 775 MHZ. Thus, our presented IME hardware architecture can process the video sequence of 4K@60FPS in real-time.