Toward data-driven architectural support in improving the performance of future HPC architectures

•An optimized hardware Thread Scheduling Unit (TSU) for future HPC architectures is proposed.•The hardware TSU was integrated into a multi-core non-coherent processor.•The processor was prototyped and evaluated on FPGA devices.•Hardware TSU is simpler and utilizes much fewer resources than Task Superscalar.•Hardware TSU is much faster than a software TSU that provides the same functionalities.