Physical Design Considerations for Synthesizable Standard-Cell-Based FPGAs

Integrating an existing commercial FPGA fabric into a system-on-chip (SoC) is challenging, due to its full-custom design methodology and use of the metal stack. Synthesizable FPGAs, built using an ASIC standard-cell methodology, have gained traction in industry and academia as a flexible alternative for embedded FPGA fabrics [1-5]. This work pertains to physical design considerations for synthesizable FPGAs, specifically those targetable by the VTR framework [1, 6]. We address the following: 1) the impact of floorplanning on the performance of, and delay variability in, the synthesized fabric; 2) extraction of component-wise delays from the standard-cell layout; 3) an examination of the spatial correlation of delays on-chip; and 4) annotation of extracted post-layout delays into VTR's timing model. In the main, this paper considers the question: in a fully synthesized standard-cell FPGA, how predictable are the delays? Our work thus contributes to the realization and modelling of high-performance standard-cell FPGA fabrics with performance predictability.