Investigation of the Trap States and $V_{\text{TH}}$ Instability in LPCVD Si₃N₄/AlGaN/GaN MIS-HEMTs with an In-Situ Si₃N₄ Interfacial Layer

A novel gate and passivation dielectric stack consisting of a thin metal-organic chemical vapor deposition (MOCVD) grown in-situ Si ₃ N ₄ (3 nm) and a thick low-pressure chemical vapor deposition (LPCVD) grown Si ₃ N ₄ (30 nm) in AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistor (MIS-HEMT) is proposed. The quality of the Si ₃ N ₄ /(Al)GaN interface and the effect on threshold voltage ( ${V}_{\text {TH}}$ ) instability and dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ in the MIS-HEMTs with/without the in-situ Si ₃ N ₄ layer are investigated by high-frequency capacitance-voltage (HFCV), quasi-static (QS) ${C}$ – ${V}$ (QSCV), time-of-fly (TOF) stress/measure, and QS ${I}_{\text {D}}$ – ${V}_{\text {DS}}$ methods. It is founded that the in-situ Si ₃ N ₄ interfacial layer is effective in improving the dielectric/III-N interface morphology. As a result, better ${V}_{\text {TH}}$ stability and lower ${R} _{ \mathrm{\scriptscriptstyle ON},\text {D}}/{R} _{ \mathrm{\scriptscriptstyle ON},\text {S}}$ ratio are observed in devices with the in-situ Si ₃ N ₄ interfacial layer due to the reduced density of traps close to the dielectric/III-N interface. Time-dependent dielectric breakdown and Weibull performance further verified that the proposed bilayer gate dielectric stack is a promising structure for the high-reliability power transistors.