ON-Resistance in Vertical Power FinFETs

This paper presents the first analytical model for the ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) in vertical power FinFETs. The model allows to extract the channel mobility and series resistance and to separate the current conduction through the bulk fin channel and the accumulation-mode metal–oxide–semiconductor (MOS) channel. The model was validated by experiments and simulations. The extracted series resistance was verified by measuring a diode fabricated in the same wafer with the FinFETs. At the same time, simulations using the extracted channel mobility and series resistance agreed well with the experiments. The model was then used to analyze a 1200 V GaN vertical power FinFET. The main ${R}_{ \mathrm{\scriptscriptstyle ON}}$ component was identified to be from the drift layer and the substrate, while the gate-modulated channel resistance only accounts for ~13% of the total device ${R}_{ \mathrm{\scriptscriptstyle ON}}$ . Our model enables parameter extraction from the dc characteristics of a single device, and therefore, provides a fast and easy way to understand, analyze, and design vertical power FinFETs. Our model can also be adjusted to allow for fast and accurate parameter extraction in other power transistors with a vertical gate-modulated channel, such as trench MOSFETs.