Influence of the Gate/Drain Voltage Configuration on the Current Stress Instability in Amorphous Indium-Zinc-Oxide Thin-Film Transistors With Self-Aligned Top-Gate Structure

The influence of ${V}_{\text {GS}}/{V}_{\text {DS}}$ condition on the current stress (CS) instability in amorphous InZnO thin-film transistors (TFTs) with the self-aligned top-gate structure is comprehensively analyzed and quantitatively validated by consolidating: 1) the ${I}$ – ${V}$ and ${C}$ – ${V}$ characteristics; 2) the extraction of density of states; 3) the decomposition of threshold voltage shift ( $\Delta {V} _{T}$ ); and 4) the computer-aided design simulation. It has been found that in a high ${V}_{\text {GS}}$ and low ${V}_{\text {DS}}$ CS condition, electron trapping into the gate insulator globally occurs. However, these effects are combined with a local electron trapping into gate insulator in the source region and the generated peroxide defects in the drain region under a high ${V}_{\text {DS}}$ and low ${V}_{\text {GS}}$ CS condition. The peroxide formation that is followed by the donor generation is clearly distinguished by the activation energy of 0.49 eV from the oxygen vacancies ionization which has been widely modeled for explaining the donor creation in amorphous oxide semiconductor TFTs.