Pseudo Expected Improvement Based-Optimization for CMOS Analog Circuit Design

In this paper, we consider the use of a new parallel efficient global optimization algorithm based on the use of the pseudo expected improvement (PEI) criterion, for the optimal design of analog circuits. A comparison with the conventional efficient global optimization algorithm (EGO) is presented. We show, via two analog circuit designs that the proposed approach gives the same optimal circuit sizing but within reduced computing time.