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SRAM On-Chip Monitoring Methodology for High Yield and Energy Efficient Memory Operation at Near Threshold Voltage

IEEE Computer Society Annual Symposium on VLSI (ISVLSI)(2019)

Seoul Natl Univ | Samsung Elect Co Ltd

Cited 1|Views23
Abstract
Low power design by near-threshold voltage (NTV) operation is very attractive since it affords to considerably mitigate the sharp increase of power dissipation. However, one key barrier for the use of NTV operation is the significant increase of the SRAM failure. In this work, we propose an on-chip SRAM monitoring methodology that is able to accurately predict the minimum voltage, Vddmin, on each die that does not cause SRAM failure under a target confidence level. Precisely, we propose an SRAM monitor, from which we measure a maximum voltage, Vfail that causes functional failure on that SRAM monitor. Then, we propose a novel methodology of inferring SRAM Vddmin on each die from the measured Vfail of SRAM monitor on the same die where Vfail-Vddmin correlation table is built-up in design infra development phase, and Vddmin can be directly derived from the measured Vfail referencing the correlation table in silicon production phase. Through experiments, we confirm that our proposed methodology is able to save leakage power by 7.43%, read energy by 3.98%, and write energy by 4.06% in SRAM bitcell array over that by applying a uniform minimum voltage for all dies while meeting the same yield constraint.
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Key words
SRAM failure,On chip monitoring methodology,Near threshold voltage,Low power,Process variation
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要点】:本文提出了一种芯片内SRAM监控方法,能够准确预测每个芯片上不导致SRAM故障的最小工作电压Vddmin,从而实现近阈值电压下的高产量和低能耗内存操作。

方法】:通过在芯片上部署SRAM监控器测量导致功能故障的最大电压Vfail,并利用设计阶段构建的Vfail-Vddmin相关性表,在硅生产阶段直接推导出每个芯片的Vddmin。

实验】:通过实验验证,该方法能够使SRAM位单元阵列的漏电流功耗降低7.43%,读取能耗降低3.98%,写入能耗降低4.06%,同时满足相同的产量约束。实验使用了特定的数据集,但未提及具体数据集名称。