12 Gbit/s three-tap FFE half-rate transmitter with low jitter clock buffering scheme

A 12 Gbit/s feed-forward equalisation (FFE) transmitter has been designed in 65 nm CMOS process. The three-tap/half-rate high-speed tap signal generation technique for the segmented FFE driver is presented. A clock buffer scheme to make the equivalent signal transition for each segmented unit contributes to a low jitter performance. The measurement results show 9.31 ps RMS jitter at 12 Gbit/s after equalisation and the horizontal eye-opening is 0.204 UI at $10^{ - 12}\; $10−12 BER. The prototype transmitter occupies $0.042\, {\rm m}{\rm m}^ 2$0.042mm2 and consumes 1.58 pJ/bit.