Parametric analysis of multipliers

With the recent advancements, low power, low area and the quickest algorithms are in high demand. In this project, an effort is made to implement modular arithmetic operations like addition, multiplication is executed. The hardware description language used is Verilog. Each of these is implemented in Xilinx ISE 14.2 with Vertex 6 as the family and in Cadence 45nm technology. The area, power and the timings of each of these algorithms are tabulated. The layouts and the RTL schematic of these algorithms are also included. A designer whose objective is to design a system with arithmetic operations can make decision-based on these parameters. Therefore he has a stable and efficient system on his hands.