A Novel Highly Reliable 12t Sram Bitcell Design

Jianwei Jiang,Dianpeng Lin,Jun Xiao,Shichang Zou

2019 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC)（2019）

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摘要

This paper presents a novel highly reliable dual port 12T static random access memory (SRAM) bitcell. Compared with the state-of-the-art soft-error-tolerant bitcells and the traditional 6T, the proposed 12T exhibits much larger read noise margin (RSNM), and also saves 85.4% read access time on average, making it much suitable for high-speed highly reliable applications.

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关键词

highly reliable SRAM, bitcell design, dual port bitcell, soft error, single event upset (SEU), RSNM

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