Self-adaptive loop for CPSs: is the Dynamic Partial Reconfiguration profitable?

Nowadays, Cyber-Physical Systems play an important role in the context of several large industries; the need for interaction with a changeable physical world leads the system adapting itself to physical changes. Adaptivity, dependability and reducing communication overheads then appear as the most wanted requirements that are moving on the adoption of the edge-computing. In turn, in this world, the demand for HW platforms able to manage increasing requirements is leading to the use of FPGAs, due to their inherent run-time reconfigurability. However, the dynamic partial reconfiguration process of an FPGA has a timing performance impact that cannot be neglected. This impact, if not well considered, can nullify the advantage obtained using a Dynamic Partial Reconfiguration. Therefore, when exploiting FPGAs with dynamic partial reconfiguration, a crucial problem is to understand whether is profitable or not to dynamically reconfigure them. In this paper, an innovative run-time manager adopting a metric to evaluate the impact of reconfiguration time is introduced, together with its validation through its usage on a basic application implemented on FPGA.