Analysis of Degradation Phenomena in Bipolar Degradation Screening Process for SiC-MOSFETs

We have developed a 3.3 kV ultra-high power density SiC power module, which was realized by fulfilment with only SiC-MOSFETs. As a countermeasure for bipolar degradation issues related to body diodes in the MOSFET structure, a high throughput screening process has been introduced. In the screening process, over 10000 chips of 3.3 kV SiC-MOSFET were evaluated. The large amount of data firstly reveals the probability distribution of the degradation phenomena and enables us to study the relationship with defect densities of the state-of-the-art SiC wafers. Furthermore, origins of the degradation were investigated by teardown analysis. The degradation is caused by the expansion or generation of bar-shaped stacking faults. It was identified that their origins are pre-existing bar-shaped stacking faults in a SiC epi-layer, a basal plane dislocation in a SiC substrate, or a closed micropipe.