Impact of Interface Trap Density of SiC-MOSFET in High-Temperature Environment
Materials Science Forum(2019)
摘要
We report the physical and electrical characterization of the inversion layer carrier and the shallow interface trap sites with n-and p-channel SiC-MOSFET in terms of high temperature electronics. This work proposes a physical model that explains the difference between Id-Vg measurement result and calculation result supposing the ideal condition with Pao and Sah double ideal in room temperature. The measurement at 500°C confirmed our model so that inversion carrier were thermally excided, they could not be easily trapped by shallow trap sites, and Id-Vg measurement result approached the ideal condition.
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