Design and Analysis of MIM Capacitor on Power Integrity Effects for HPC and Network Applications

In this work, we investigate power integrity (PI) effects of using metal-insulator-metal (MIM) capacitors for high power applications. As transistor density for integrated circuitry increases at advanced process nodes, the PI management of high power applications becomes more challenging. MIM capacitor offers a possible solution to overcome these issues by acting as a fast response charge tank. The MIM capacitor mentioned here was designed for high-power IP with about 2 mW/um ² at 1GHz. Based on the simulation results, PI properties was analyzed by the designed MIM capacitor considering offchip parameters. As a result, it is demonstrated that the worst and the average of dynamic voltage drop (DVD) are improved by 22.5% and 42.5%, respectively when compared to the case without MIM capacitors. In addition, usage of MIM capacitors reduces the package decap requirement by 54% to meet same target voltage drop. Consequently, the usage of MIM capacitor is advantageous to make high power IP blocks stable in an integrated chip. Thus, it is expected to develop the design methodology of effective MIM usage and investigate system-level optimal capacitor configuration considering various decoupling capacitors such as on-die capacitor, MIM capacitor, and package decoupling capacitor.