Minimization Of Dead Time Effect On Bridge Converter Output Voltage Quality By Use Of Advanced Gate Drivers
2019 10TH INTERNATIONAL CONFERENCE ON POWER ELECTRONICS AND ECCE ASIA (ICPE 2019 - ECCE ASIA)(2019)
摘要
This paper presents a voltage-controlled multistage gate driver topology for delay time minimization that improves the converter output voltage quality while supplying a motor load. Three gate driver topologies for SiC MOSFETs are compared based on their dead time requirement in a bridge leg converter. Experimental results of the gate driver delay times are reported and are used as input to a simulated motor drive application. Results show that turn-off delay times can be reduced by up to 74 % for the multistage driver compared to the conventional counterpart when the rate of change for the converter voltage output is limited to 10 V/ns. Furthermore, minimizing the dead time increases the linearity region of the output voltage from the converter by 1.8 % to 3.8 % and reduces the current THD in the linear region by up to 7.7 % when switching at 15 kHz.
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关键词
Gate driver,wide band-gap,SiC MOSFET,dead time
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