A Method Of Improving The Performance Of Hybrid Reconfigurable Hardware

The high processing speed and reconfigurable features of FPGA (Field-Programmable Gate Array) make it the first choice for acceleration chip. Currently, the CPU/FPGA hybrid architecture is a research hotspot in improving hardware processing speed. Many companies have investigated in related researches. However, the current researches have not solved the coordination problem between CPU and FPGA in this architecture. The Communication efficiency problem between CPU and FPGA is the key to the failure of hardware performance. Some of the current researches are mainly to optimize the communication protocol between CPU and FPGA to improve data transfer rate. This paper proposes a different method to reduce the frequency of communication between CPU and FPGA for this problem. The processing speed of the architecture is improved by simplify communication between the CPU and the FPGA. This approach reduces communication frequency between the CPU and the FPGA by splitting the software into hardware master thread and slave threads that can run independently run on the FPCA. The CPU only needs to configure the FPGA at the beginning and retrieve the result from the FPGA at the end. No communication is required during FPGA running, thereby reducing unnecessary communication waste.