A Comparator-Reused Dynamic-Amplifier For Noise-Shaping Sar Adc

This paper presents a high-speed high-gain dynamic amplifier which can also be reused as a comparator for a noise-shaping (NS) successive-approximation-register (SAR) analog-to-digital converter (ADC). By modifying a strong-arm latch, this dynamic amplifier can achieve a high speed of comparison and dynamic amplification, which is crucial to a high-performance NS SAR ADC. The prototype is designed in 28 nm CMOS process. It realizes the comparison speed of 0.2 ns and 8 times dynamic amplification in 0.9 ns with 0.6 pF single-end capacitance load. Meanwhile, the noise floor is 11 nV/root Hz and the THD is -76.5 dB with the power consumption of 56 mu W averagely.