Research on the impact of different benchmark circuits on the representative path in FPGAs

The transistor-level optimization of FPGAs faces a huge challenge due to the programmability. We don't know what kinds of end-user's circuit will be implemented on the FPGA. This means that the critical path is unknown at design time. To handle this issue, academic community creates a representative path which will be used during optimization. This path is the shortest register to register path within an FPGA that contains all unique components. However, no research has analyzed how different reference circuits can affect the representative path. In order to explore this issue, we obtained statistics of sub-circuit usage of the critical path of different benchmarks. sub-circuit includes interconnect circuits and logic resources. This paper compares the two aspects of the representative path and each critical path: sub-circuit utilization rate and the delay of paths. For the first aspect, result shows that the sub-circuit utilization rate on the representative path can indicate the sub-circuits utilization rate on critical path in different benchmark circuits. For the second aspect, the critical path delay of FPGA fluctuates between -10.6% and +8% of the representative path delay when implementing different benchmark circuits. We found that under the premise of selecting a large number of typical benchmark circuits, the representative path delay can well represent the overall timing performance of FPGAs.